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Design
For Testability and for Built-In Self Test Course (ICs, Boards,
Systems 3-days)
January 23-25, 2017 in Los Angeles, CA
Cost-Effective
Strategies for Improved Time to Market with DFT and JTAG/Boundary
Scan
IPC APEX Professional Development Course
February 12, 2017 2:00 - 5:00 PM, San
Diego, CA
Design for Testability Strategies for Today's Circuits
Presented for
the Los Angeles/Orange County Chapter
March 16, 2017 9:00 AM - 4:30 PM in Garden Grove,
CA
How to Design for Testability (DFT) for Today's Boards and Systems
A Surface Mount Technology Association (SMTA) Webtorial
Presented on July 12 and July 14, 2016
Taped Version Available Here
Introduction to Automatic Test System Software Standards and to
Automatic Test Markup Language (ATML)
Design For Testability and for Built-In Self Test Course for Boards
and Systems (2-days)
in
Barcelona, Spain
Date To Be Determined
Pre-Purchase Course Notes for
Design
For Testability and for Built-In Self Test Course (ICs, Boards,
Systems 3-days)
Receive full refund when you attend
Our Leadership at
AutoTestCon in Washington, DC, including our 1/2 day Diagnostics and
Design for Built-In Test Tutorial on September 12-15, 2016 at The Disneyland Hotel in Anaheim, CA
ANY OF OUR COURSES AT YOUR FACILITY AT
YOUR CONVENIENCE
Testimonial from Juan Jose Vicente Navarrete
Hardware Design Manager at BQ in Spain
I am an electronic designer and I was one of your
attendees at your DFT and BIST course in Barcelona... This course
opened my eyes of built-in self-test as one of the most important
ways to differentiate our boards from others from our competitors.
Enabling our boards to test themselves -while the user does not
notice it-, can help us to improve our time-back-to-home of our
aftersales department which would increase our users'
experience…Thank you Louis Y. Ungar!
View All Our Courses
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held, OnLine, OnSite or Privately
held
Recorded Presentations
Check Out Our
Products
New Product Releases
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Announcements about A.T.E. Solutions, Inc.
Louis Ungar shares Best Management Paper award at AutoTestCon 2015
with Dr. Mustafa iLARSLAN, Col. Turkish Air Force for
"Mitigating the Impact of False Alarms and No Fault Found Events in
Military Systems"
We are continuing our Design for Testability (DFT) effort
towards the IPC's Design for eXcellence (DFX) standard,
IPC-2231
IEEE-1687 known as the IJTAG (Internal JTAG) is approved and
as balloters of the standard we are determined to help our
students and clients put it to good use.
We have just completed a 3-day on-site Test, ATE and
Testability course for the US Navy (Marine Corps) at Cherry
Point, NC. Great class!
Links through
LinkedIn
See Louis Ungar's LinkedIn Profile
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Join the No Fault Found Solutions Group on
LinkedIn |
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