Analog Test and Fault Isolation

What you will learn:
Digital test solutions do not address the unique problems faced by analog test. In fact, many high-speed digital tests require understanding of analog failure modes and test techniques. There are many problems that you will encounter when you try to test analog circuits with an ATE. The course will show how accuracies and resolutions can affect your test results. You will also learn to deal with analog simulation and fault simulation issues.

The course introduces how analog is tested and proceeds to characterize analog failures. It looks at the role of D/A and A/D converters and their influence on measurements. The course also discusses fault isolation and how ATE can meet this challenge. It will cover standards such as the IEEE-1149.4 Mixed Signal Testability and the IEEE-1149.6 IEEE 1149.6-2015 – IEEE Standard for Boundary-Scan Testing of Advanced Digital Networks. We will also explore discussions of analog test being standardized by IEEE-P2427 Standard for Analog Defect Modeling and Coverage and IEEE-P1687.2 Standard for Describing Analog Test Access and Control.

Who should attend:
Anyone who tests analog and mixed signal circuits. Basic understanding of electrical circuits is required to follow the material.

Course Outline

Introduction to the Analog World

  • Measurement Problems
  • Stimulus Problems
  • Speed Problems
  • Automation Problems
  • Standard for Analog Defect Modeling (IEEE-P2427)

Analog Testing

  • Measurements Criteria
  • Failure Analysis
  • Digital Signal Processing
  • Fixturing Considerations

Analog Fault Isolation

  • Concept of the Active Element Group (AEG)
  •  In-Circuit Test Methods

Analog Simulation

  • Using ISPICE
  • Mathematical Modeling
  • Tolerances and Accuracies
  • Analog Automatic Test Generation

Analog Standards

  • Introduction to boundary-scan
  • Mixed-Signal Boundary-Scan and the IEEE-1149.4
  • AC EXTEST and differential transmission using IEEE-1149.6
  • IEEE-P1687.2 Standard for Describing Analog Test Access and Control
    • Instrument Connectivity Language (ICL) for analog
    • Procedure Description Language (PDL) for analog

Summary and Conclusions

  • Questions/Answers


Louis Y. Ungar
Louis Y. Ungar, President of Advanced Test Engineering (A.T.E.) Solutions, Inc. holds a B.S.E.E. and Computer Science degree from UCLA and has completed course work towards a M.A. in Management. As a test engineer, Mr. Ungar designed automatic test equipment (ATE), created hundreds of test programs for dozens of ATEs. As a design engineer he designed payload systems for the Space Shuttle, eventually leading a team of designers. With both engineering and management experience in test and design, Mr. Ungar founded A.T.E. Solutions, Inc. in 1984, a highly respected test and testability consulting and educational firm. Mr. Ungar serves as Testability Committee Chair for the Surface Mount Technology Association (SMTA), as Consultant to the American Society of Test Engineers (ASTE), the founding President of the Testability Management Action Group (TMAG) and various test and testability groups of the Institute of Electrical and Electronics Engineers (IEEE). He has recently balloted on the IEEE-1149.1-2013 and the IEEE-1687. He also developed the Testability section of a Design for Excellence (DFX) Guideline by the IPC to be published in 2018.

Other qualified A.T.E. Solutions, Inc. instructors may teach this course.


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On-Site Webinar:
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