Design for eXcellence

What you will learn:
This course will teach you how to design a product that is manufacturable, testable, highly reliable, safe, useable, electromagnetically compatible, maintainable and supportable. In short, an electronic product that not only functions but is made to be of excellent value to you and to your customer. While the coverage is for electronics many of the principles apply to mechanical products as well.

Design for Defect-free Manufacturability, for Testability, for Useability, for Reliability, for Extreme Environments, for minimizing Maintainance and for Supportability is a necessity in today’s complex electronics and life cycle costs savings. This course combines the various -ilities, using experts from various fields, so that you can plan a design for excellence.

Who should attend:
Design engineers and managers will find this course enlightening. Professionals of various disciplines – manufacturing, test, reliability, maintainability and others will also learn how to incorporate into the design their disciplines. Marketing managers will improve customer relations by communicating the tenets of this discipline.

Course Content

Design for Excellence (DfX) – Bringing all the–abilities together


  • What Constitutes DFX
    • Reliability
    • Safety
    • High Return on Investment
    • Electromagnetic Compatibility
    • Usability
    • Testability
    • Built-In SelfTest
    • Manufacturability
    • Maintainability
    • Systems Integration
    • Diagnosability
    • Others
  • Failure Mode, Effects, and Criticality Analysis (FMECA)
  • A Common Platform for all the -abilities

Design for Reliability

  • New paradigms in design for reliability
  • Designing products for long life (durability)
  • Design FMECA for avoiding failures
  • Accelerated life testing models
  • Weibull analysis for life test data

Design for Safety

  • Evidence-based safety design methods
  • Hazard analysis and risk mitigation techniques
  • Active safety vs. passive safety
  • Fault Tree Analysis for Robustness
  • Verification and Validation for safety
  • Testing for safety

Design for Manufacturability

  • Customer Satisfaction Requirements
  • Functional Responsibilities of DFM
  • Concurrent Engineering
  • Process FMECA for avoiding manufacturing defects
  • Good Supplier Specifications
  • Early Supplier Qualification
  • Defining the Process
  • Six Sigma and Statistical Thinking
  • Understanding and Controlling Process Variation
  • Understanding and Implementing a World Class Quality System
  • Process Characterization Concepts
  • Evaluating Printed Circuit Board Designs
  • The “Black Belt” Quality Certification Program
    • Improve Process Availability and Yield
    • Use of Process FMECA to reduce vulnerability in manufacturing
    • Reliability centered maintenance

Design for Usability

  • Usability Terms
  • Usability Engineering
  • Usability Documentation
  • Usability Measures
  • False Alarms – A consequence of poor usability

Automatic Testing and ATE Strategies

Design for Testability

  • What is Design for Testability?
  • Quality as a Function of Yield and Test Coverage
  • Fault Models
  • Effect of Time-to-Market On Profits
  • Approaches to Design for Testability
    • Ad Hoc Design for Testability
    • Structured Design for Testability
  • Design for Testability Attributes
    • Controllability
    • Observability
    • Others
  • Evaluating Designs for Testability

    • Dependency Models
    • Testability Checklists
    • Other Testability Analysis tools
  • Structured Design for Testability
  • Technical Goals of Testable Designs
  • General Structure of Scan
  • Boundary Scan Structure (JTAG/IEEE-1149.1)
  • Boundary-Scan Operational Modes
  • Mixed Signal Boundary Scan – IEEE-1149.4
  • AC EXTEST Using the IEEE-1149.6
  • Verification and Validation for Testing Effectiveness
  • Other Testability Guidelines and Organizations
    • SMTA Testability Guidelines
    • Testability Management Action Group (TMAG)
    • Other IEEE-1149.x and 1687.x

Design for Built-In Self Test

  • Technical Approach to BIST
  • Forms of Built-In Self Test
    • Continuous Monitoring (CM)
    • Initiated Bit (I-BIT)
    • Operational Readiness Test (ORT)
  • Elements of a BIST Architecture
  • BIST Classification
  • BIST Using Set/Scan Logic
    • Signature Analyzer
    • Pseudo-Random Signal Generator
    • Linear Feedback Shift Register from Scan Cells
    • Built-In Logic Block Observer (BILBO)
  • BIST Signal Generation tools
  • BIST Response Collection tools
  • BIST Architectures
  • Built-in Test (BIT) Software
  • Why use BIT Software?
  • BIT Software Considerations
    • Guidelines for Software BIT
    • Selecting a Software Language
    • Performance Monitoring Software
  • Failure Analysis Software
  • BIT False Alarms
  • Evaluating BIT
  • BIT Specification

Design for Maintainability

  • MIL-HDBK-470B for program requirements
  • MIL-HDBK-472 for maintainability prediction
  • The Support Concept –
    • Design for Operational Readiness
  • Preventive vs. Corrective Maintenance
  • Human Engineering
  • Design for Maintainability Requirement
  • Interaction between Human and Product
    • Design choices of switches, knobs, levers, wheels, etc.
    • Anthropometrics 
  • Testability in Maintenance
  • Diagnostics in Maintenance
  • Built-In Test in Maintenance
  • Prognostics Health Monitoring (PHM)
  • Maintainability Analyses
    • Equipment Downtime Analysis
    • Maintainability Design Evaluation
    • Failure Mode Effects and Criticality Analysis (FMECA)
    • Testability Analysis
    • Human Factors Analysis

Design for Diagnosability

Other –abillities

Bringing it All Together Under a Single Common Criterion

Summary and Takeaways


Louis Y. Ungar, President, A.T.E. Solutions, Inc.
Louis Y. Ungar, President of Advanced Test Engineering (A.T.E.) Solutions, Inc. holds a B.S.E.E. and Computer Science degree from UCLA and has completed course work towards a M.A. in Management. As a test engineer, Mr. Ungar designed automatic test equipment (ATE), created hundreds of test programs for dozens of ATEs. As a design engineer he designed payload systems for the Space Shuttle, eventually leading a team of designers. With both engineering and management experience in test and design, Mr. Ungar founded A.T.E. Solutions, Inc. in 1984, a highly respected test and testability consulting and educational firm. Mr. Ungar serves as Testability Committee Chair for the Surface Mount Technology Association (SMTA), as Consultant to the American Society of Test Engineers (ASTE), the founding President of the Testability Management Action Group (TMAG) and various test and testability groups of the Institute of Electrical and Electronics Engineers (IEEE). He has recently balloted on the IEEE-1149.1-2013 and the IEEE-1687. He also developed the Testability section of a Design for Excellence (DFX) Guideline by the IPC to be published in 2018.

Joe Belmonte, Principal Consultant, ITM Consulting
Joe has been a process engineer and process engineering manager in the electronic manufacturing industry for over 30 years with experience in all aspects of electronic product assembly operations.  He holds an Associate Degree in Mechanical Design from Wentworth Institute in Boston and a Bachelor of Science Degree in Operations Technology from Northeastern University in Boston . From 2007 to 2009 he worked at Bose Corporation as the Manager of Advanced Manufacturing Engineering and as a Supplier Engineer and was responsible for the development and implementation of all new electronic manufacturing processes at Bose Manufacturing Operations and the training of all Bose Electronic Manufacturing/Process Engineers.  From 1995 to 2007 Joe was a Consultant at Cookson Electroics/Speedline Technologies Performance Solutions Group and Project Manger at Speedline Technologies Advanced Process Group where he worked with customers on quality and cycle time improvement projects including performing detailed assessments of their entire manufacturing operation to identify strengths and opportunities for improvement.  As Project Manager at Speedline Technologies Joe’s primary responsibilities included managing advanced process development projects (Lead Free Process Development Program, High Volume Fuel Cell Process Development Program, and Miniature Component Assembly Process Development), working with customers on process improvement programs, and providing process training.  From 1978 to 1995, Joe worked as a process engineer and process engineering manager at Motorola ISG .  Joe has been a senior member of the Society of Manufacturing Engineers (SME) for over 20 years, has served as a member of the Electronic Manufacturing Association of SME Board of Advisors and currently serves as a member of the SMTA Board of Directors.

Dev Raheja, International Risk Management Consultant
Dev Raheja, is an international consultant and trainer in new product development since 1981. Prior to this he served in management positions at Booz-Allen & Hamilton, Inc., General Electric, and Cooper Industries. He is a world leader in Design Assurance and is credited with turning around a major Division of a large corporation from going out of business to achieving Number One market position. Since then he has rescued several businesses. His clients include General Motors, Harley-Davidson, Eaton, Intel, Northern Telecom, IBM, Siemens, Nissan, NASA, Boeing, Mattel, Warner Lambert, Johnson & Johnson, Lockheed-Martin, British Telecom, Ford, Apple Computer, and U.S. Navy. He served as Adjunct Professor at the University of Maryland for its Ph.D. program in Reliability Engineering during 1994-99.. e serves as Adjunct Professor at the University of Maryland for its graduate programs in Reliability Engineering and Mechanical Engineering. He has received several awards including the Scientific Achievement Award and Educator-of-the-Year Award from the System Safety Society. He is an author of McGraw-Hill best technical sellers Assurance Technologies: Principles and practices” (1991). He has taught courses Designing for Reliability, Designing for Safety, and Developing Innovation Skills. In 2012 he wrote the book Design for Reliability (Wiley).


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