Design for Testability (DFT) and Built-In Self Test (BIST): Not only for Test Engineers

May 26, 2020 (May 27, 2020 in Asia)

***This time FREE for a limited number of attendees due to Coronavirus Pandemic ***

Choose your time:

Starting: 9 AM Pacific, 16:00 (UTC) and
also at 9 PM Pacific, (May 27 Noon in Singapore)

Note: The 9 AM class is almost full.  If you can, please select the 9 PM Webinar

Length:  45 minutes 

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What you will learn:

Why do we need DFT and BIST?  The answer is economic and common sense.  If something is NOT testable, you can’t ever make sure it is working properly and obviously selling an untestable product is risky, if not economically suicidal.

This short webinar – intended to make non-test engineers aware of DFT and BIST techniques – will provide you with an explanation that you can follow without all the technical details test professionals need to know.  Nonetheless, you will learn JTAG, Boundary Scan, Built-In Self Test without having to become a test engineer.  It is intended for Managers and Engineers of various disciplines who have heard test engineers appealing for DFT and BIST but found the rationale too detailed and too technical to really follow the arguments.  All technical issues will be thoroughly explained so that non-technical attendees don’t get lost, yet technical attendees also learn applicable principles.  Test engineers who attend will learn a good way to explain the concepts to their colleagues but do bring or send others to this webinar.

Course Content:

  • Different tests and different points in the product life cycle
    • Automatic Testing and ATE
  • The cost of test vs. the costs of no test
  • Measuring the defect detection of a test and test escapes
  • Exponential growth in circuitry and in defects to detect
  • What can we do with undetectable and untestable defects?
    • Back to design
  • DFT assessment and tools for designers
  • DFT techniques explained:
    • Observability, Controllability and Diagnosability
    • Scan and Boundary Scan (JTAG/IEEE-1149.x) and beyond
  • Built-in Self Test – an extension of DFT
  • Built-in Self Repair (BISR) – the new paradigm
  • Profiting from DFT, BIST and BISR

Who should attend:

While the course does contain topics involving electronics, it is explained in a way that a non-technical audience can follow.  This is not to say that Design and Test Engineers would not benefit, but they will probably need more detailed follow-ons.  The main benefit of this course will be to managers, quality assurance, marketing and others who will be able to understand why DFT and BIST are important parts of their products.

Instructor:

Louis Y. Ungar is a leading expert in Design for Testability, having been active in developing standards such as IEEE-1149.x, IEEE-1687, the Surface Mount Technology Association (SMTA) Testability Guidelines and most recently the IPC-2231 Design for eXcellence (DFX) standards.  He is now working on Analog Testability standards IEEE-P1687.2, IEEE-P2427 and System level SJTAG IEEE-P2654.  For Mr. Ungar’s general biography, see https://besttest.com/courses/instructors/

Public Webinar:
Date: May 26, 2020
Length: 45 min (Normally 90 minutes)
Price:  ***This time FREE for limited number of attendees due to Coronavirus Pandemic *** (Normally $99.00/person)
» Register for 9 AM Pacific Time

» Register for 9 PM Pacific Time (May 27 Noon in Singapore)

 Note: The 9 AM class is almost full.  If you can, please select the 9 PM Webinar

Follow with a Traditional Course:
Date: TBD
Length: 2-days
Location: Los Angeles
Price: $1,995/person
» Register
» Reserve

Find out how we can bring this webinar to your facility (On-Site):
Date: Your choice
Length: 1 x 90 min modules
Location: Via Internet
Price: Request a Quote