Design for Testability and for Built-in Self Test

What you will learn:

In this comprehensive course you will learn all aspects of Design for Testability (DFT), from what it is, why you might need it, why someone would object to it, and what it can and cannot accomplish. You will learn how today’s technology has become elusive to certain failure modes and how important it is to expose them through more testable designs. This class will encompass DFT techniques for ICs, ASICs, SoCs, FPGAs, boards, systems, and even prognostic health management. First you will learn some simple techniques to enhance observability and controllability. You will learn how you can access hundreds of internal points with as few as four additional edge connector pins. You will learn specific guidelines for both digital and analog circuit testability. You will learn structured testability techniques, such as internal and boundary-scan. You will come away with a deep understanding of the IEEE 1149.1 (JTAG) standard’s operation, use and even its limitations. You will also learn later standards, such as IEEE-1149.4, .6, .7 as well as IEEE-1500, 1532, 1581 and 1687. You will also learn some new techniques in testability, including IDDQ testing and I/O Mapping. In the second part of the course, you will learn what built-in [self] test (BIST) is and how it can be specified. You will learn structures such as linear feedback shift registers (LFSRs), signature analyzers, and pseudo-random signal generators. With these building blocks you will be able to evaluate a number of BIST architectures for Logic BIST and Memory BIST. You will learn BIT Software techniques and consider the effect false alarms have on BIT. You will finally be able to specify BIT for your products and look at the possibilities of BIT taking over some of the ATE functions.

This is really two courses combined into one. The first part, Design for Testability provides the guidelines necessary to improve circuit design from a test perspective. It includes simple and easy-to-implement ad-hoc testability guidelines. Then the course looks at more sophisticated structured approaches to testability that can be placed into ICs and boards. Special emphasis will be given to boundary-scan, the (JTAG) IEEE-1149.1. Analog circuit testability builds on the IEEE-1149.1 and is now the Mixed-Signal testability standard, designated as IEEE-1149.4. We examine this standard as well as the IEEE-1149.6 standard for AC Signal and transmission. We will look at other related standards in development, such as the IEEE-1532, IJTAG and SJTAG. The second part of the course will cover Built-In Test. Starting with classification of Built-In Test approaches, the course introduces the building blocks of built-in self test (BIST) architectures. The course then examines some of these architectures, including Random Test Socket (RTS), the Built-In Logic Block Observer (BILBO), the Cyclic Analysis Testing Systems (CATS), the Built-In Test Exerciser and Sensor (BITES), and others. BIT software is also covered and a discussion on BIT false alarms is included. Finally, a hierarchical approach to BIT is examined, which offers a reduction if not elimination of ATE in both a manufacturing and maintenance environment. Towards that end we will learn about IEEE-1687 and test reuse and plan the paradigm change in test.

Who should attend:
This is a design course, intended for designers and for those who motivate them for testability, such as test engineers. Managers concerned with testability issues will also find this course useful. Anyone interested in boundary-scan (JTAG/IEEE-1149.1) will agree with many of our graduates who called this the best course available on the subject. Since Built-In Test is becoming an issue of concern for top management as well as to marketing, this course – though a bit on the technical side – does examine applications for BIST in a product.

Course Contents 

Introduction (For 3-day Courses Only)

  • Test Concepts and Automatic Testing
  • Definitions
  • DFT ? Why, What, Who, When?
  • Built-In Test (BIT), Embedded Test and Built-In Self Test (BIST)

Design for Testability Attributes

  • Controllability
  • Observability
  • Others
  • Testability Metrics including
    • SCOAP
    • FAM and STRID

Structured DFT for ICs

  • Fault Models and Simulation
  • Automatic Test Pattern Generation (ATPG)
  • Scan Concepts including MUX DFF and LSSD
  • Random Access Scan
  • Test Compression
  • Low Pin Count Test (LPCT)
  • At-Speed Testing Using Scan
  • Scan Standards for ICs (IEEE-1500, 1149.7)
  • IDDQ Testing
  • Logic BIST
  • Memory BIST

Board Level DFT and BIST

  • Ad Hoc Design for Testability
  • Electronic Manufacturing Test Strategies
  • Boundary Scan (JTAG/IEEE-1149.1)
  • JTAG and IEEE-1149.4, .6, .7
  • PCOLA/SOQ for various test strategies
  • Probing and Fixturing Guidelines
  • Flying Probe Testability Guidelines
  • Vectorless Test and the IEEE-1149.8.1
  • Automatic Optical and X-Ray Inspectability
  • Electrical Design Guidelines

Partitioning to Functionally Independent Sub-Systems

  • Power Level Partitioning
  • System Level Partitioning
  • Mechanical Partitioning
  • Partitioning Using Degating Circuits
  • Analog DFT and BIST
  • IO Mapping
  • Towards a Contactless Board Level Test

Built-In Self Test (BIST)

  • BIST Classification
  • Continuous Monitoring (CM)
  • Initiated Bit (I-BIT)
  • Operational Readiness Test (ORT)
  • BIST Using Error Detection Codes
  • Signature Analyzer
  • Pseudo-Random Signal Generator
  • Linear Feedback Shift Register from Scan Cells
  • Built-In Logic Block Observer (BILBO)

BIST Architectures

  • Random Test Socket (RTS)
  • Self-Testing Using MISR and Parallel SRSG (STUMPS)
  • Centralized and Separate Board-Level BIST
  • Built-In Evaluation & Self Test (BEST)
  • Concurrent BIST Architecture
  • Simultaneous Self Test (SST)
  • Cyclic Analysis Testing Systems (CATS)
  • Circular Self Test Path (CSTP)
  • Redundancy BIT
  • Wrap-around BIT
  • Analog BIST
  • Voltage Summing BIT
  • BIT and BIST Specification

System Level DFT and BIST

  • System Level Functional Test
  • Diagnosis and Integrated Diagnostics
  • Failure Mode Effects (Criticality) Analysis
  • Guidelines of MIL-STD-2165
  • Built-In Test Software
  • Dependency Modeling
  • SJTAG and the IEEE-1149.x for System Repair
  • False Alarms and Incorrect Isolation

Testability Standards and Guidelines (For 3-day Courses Only)

  • TMAG/Surface Mount Technology Association Testability Guidelines
  • MIL-HDBK-2165
  • The Testability Director

Hierarchical DFT and BIST

  • Hierarchical Test and Repair
  • DFT and BIST Repair Strategies
  • IEEE-1687 and related DFT

DFT and BIST Economics

  • Time to Market Model
  • Repair or not?
  • What are we really saving in financial terms?
  • Justifying and selling DFT and BIST
  • Managing DFT and BIST

Summary and Advanced Concepts to Ponder

  • Remote Test and Diagnoses
  • Prognostics and Health Management
  • How DFT and BIST affect security and counterfeiting
  • Built-In Self Repair


Louis Y. Ungar
Louis Y. Ungar, President of Advanced Test Engineering (A.T.E.) Solutions, Inc. holds a B.S.E.E. and Computer Science degree from UCLA and has completed course work towards a M.A. in Management. As a test engineer, Mr. Ungar designed automatic test equipment (ATE), created hundreds of test programs for dozens of ATEs. As a design engineer he designed payload systems for the Space Shuttle, eventually leading a team of designers. With both engineering and management experience in test and design, Mr. Ungar founded A.T.E. Solutions, Inc. in 1984, a highly respected test and testability consulting and educational firm. Mr. Ungar serves as Testability Committee Chair for the Surface Mount Technology Association (SMTA), as Consultant to the American Society of Test Engineers (ASTE), the founding President of the Testability Management Action Group (TMAG) and various test and testability groups of the Institute of Electrical and Electronics Engineers (IEEE). He has recently balloted on the IEEE-1149.1-2013 and the IEEE-1687. He also developed the Testability section of a Design for Excellence (DFX) Guideline by the IPC to be published in 2018.


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